1. Technical Field
This disclosure relates to semiconductor fabrication and more particularly, to an improved method for etching back buried strap polysilicon for deep trench capacitor storage node formation.
2. Description of the Related Art
Semiconductor memory devices such as dynamic random access memories (DRAMs) include capacitors accessed by transistors to store data. Deep trench (DT) capacitors are among the types of capacitors used in DRAM technology. Deep trench capacitors are typically buried within the semiconductor substrate. To connect the deep trench capacitor to a transfer device (access transistor) a buried strap contact has to be formed. The buried strap contact formation is done by recessing a DT oxide collar to form a divot or recessed portion and subsequently filling the collar divot with doped polysilicon, which is also used for a storage node formed in the deep trench. The polysilicon deposition is performed by a chemical vapor deposition (CVD) process, i.e., all of the exposed surface is covered by a polysilicon layer. Prior to the polysilicon deposition a high temperature nitridation is typically performed to form an ultra-thin nitride layer. This nitride layer reduces defect generation from the buried strap interface which is the root cause for variable retention time (VRT) problems.
Since the polysilicon is only needed in the divot, the other trench parts have to be cleaned again (i.e., polysilicon removal). This process is called the buried strap poly etchback (BSPE). Currently, this BSPE process is done by means of a chemical dry etch process (CDE) particularly a dry, isotropic reactive ion etch (RIE) process which removes a constant amount of polysilicon.
Disadvantages of this process include:
1. The process is non-selective to silicon of the deep trench sidewall. Therefore, overetch into the crystalline silicon is possible resulting in poor control for the process.
2. The process leaves poly silicon in a pad oxide undercut which is formed in prior process steps. The pad oxide is typically formed on a top surface of the substrate for protection of the surface for later gate oxidation. A portion of the pad oxide adjacent the deep trench is typically etched. When polysilicon is formed, these etched portions fill with polysilicon. This polysilicon causes gate oxide reliability problems especially if vertical devices (i.e., access transistors on the DT sidewall) are formed.
3. The RIE tool is a single wafer tool (poor throughput). Only one wafer at time is typically processed with this tool.
Therefore, a need exists for an improved method for a buried strap polysilicon etch back process. A further need exists for a buried strap polysilicon etch back process which provides higher throughput and better performance characteristics over the prior art.